1. Field of the Invention
The present invention relates, in general, to testing techniques and, more particularly, to a method for testing a plurality of functional circuit blocks, wherein each of the functional circuit blocks is designed as an existing semiconductor integrated circuit.
This claims priority under 35 USC §119 to Japanese patent application Serial Number 371925/2001, filed Dec. 5, 2001, the subject matter of which is incorporated herein by reference in its entirely for all purposes.
2. Description of the Related Art
In recent years, a system LSI comprises many functional circuit blocks. The functional circuit block which is a core of the system LSI, is called as intellectual property (IP), macro cell or so on. The IP is a block which is designed in the state of hardware or software and executes a specific operation.
A conventional method for testing the functional circuit blocks in the system LSI sets a plurality of test groups each comprising a plurality of the functional circuit blocks to be tested simultaneously, using a combination of a parallel access method and a serial access method. The conventional method tests the test groups in turn. The concept of the parallel access method is shown in FIG. 14. As shown in FIG. 14, each of the input and output terminals of each of IP 1401 and 1402 connects with the outer terminals of the system LSI 1400 with one-one relation. The parallel access method tests a plurality of IP parallel using the outer terminals of the system LSI, by inputting a signal to IP from the outer terminals directly and observing an output signal output by the outer terminals directly. The concept of the serial access method is shown in FIG. 15. As shown in FIG. 15, there are a serial-parallel converter 1501 and a parallel-serial converter 1502 between the outer terminals of the system LSI 1500 and the input and output terminals of IP 1503 and 1504. The serial access method tests a plurality of IP serially using the outer terminals of the system LSI, by inputting a signal to IP from the outer terminals through the serial-parallel converter 1501 and observing an output signal output by the outer terminals through the parallel-serial converter 1502.
An operation of the conventional method for testing the functional circuits in the system LSI will be described with reference to FIG. 16. The vertical axis shows the range of the number of pins of the system LSI necessary for testing. The horizontal axis shows test time necessary for testing. Six functional circuit blocks IP(A)–IP(F) are shown in FIG. 16. A vertical length of each functional circuit block is indicative of the number of pins of the system LSI necessary for testing. A horizontal length of each functional circuit block is indicative of test time necessary for testing.
The conventional test method divides the functional circuit blocks into a plurality of test groups. In FIG. 16, the functional circuit blocks are divided into four test groups. A first test group comprises the functional circuit blocks IP(A) and IP(B). A second test group comprises the functional circuit blocks IP(C) and IP(D). A third test group comprises the functional circuit block IP(E). A fourth test group comprises the functional circuit block IP(F).
The conventional test method tests the functional circuit blocks by test groups. First, the first test group is tested. Next, the second test group is tested, after the test in the first test group is finished. Correspondingly, the third test group is tested, after the test in the second test group is finished. The fourth test group is tested, after the test in the third test group is finished.
However, each of the functional circuit blocks in each test group does not always have the same test time as the other functional circuit blocks in the corresponding test group. The test time of the functional circuit block IP(A) is longer than that of the functional circuit block IP(B). The non-used pins of the system LSI for testing exist uselessly, from the time of finishing the test in the functional circuit block IP(A) until finishing the test in the functional circuit block IP(B). The testing of the second test group can not start immediately after the test of the functional circuit block IP(B) is finished, because the test in the functional circuit block IP(A) has not been finished yet. Therefore, the conventional test method does not use the non-used pins of the system LSI effectively.